Flavien Solt
PostDoc

flsolt@ethz.ch
☞ Office: ETZ-H90
Google Scholar

I am a postdoctoral researcher in the Computer Security Group at the Department of Information Technology and Electrical Engineering (D-ITET) at ETH Zürich. My research explores innovative techniques for securing computer hardware.

Before, I completed a PhD with Prof. Kaveh Razavi on the topic of software-inspired techniques for digital hardware security, preceded by a D-ITET MSc at ETH Zürich focusing on digital hardware design, that followed an Ingénieur Polytechnicien MSc curriculum in computer science and mathematics.

Teaching

  • Computer Engineering, BSc 2022-24.

Publications

generated by bibbase.org
  2025 (2)
Encarsia: Evaluating CPU Fuzzers via Automatic Bug Injection. Matej Bölcskei; Flavien Solt; Katharina Ceesay-Seitz; and Kaveh Razavi. In USENIX Security, August 2025.
Encarsia: Evaluating CPU Fuzzers via Automatic Bug Injection [pdf]Paper   Encarsia: Evaluating CPU Fuzzers via Automatic Bug Injection [link]URL   link   bibtex   156 downloads  
Lost in Translation: Enabling Confused Deputy Attacks on EDA Software with TransFuzz. Flavien Solt; and Kaveh Razavi. In USENIX Security, August 2025.
Lost in Translation: Enabling Confused Deputy Attacks on EDA Software with TransFuzz [pdf]Paper   Lost in Translation: Enabling Confused Deputy Attacks on EDA Software with TransFuzz [link]URL   link   bibtex   210 downloads  
  2024 (5)
𝜇CFI: Formal Verification of Microarchitectural Control-flow Integrity. Katharina Ceesay-Seitz; Flavien Solt; and Kaveh Razavi. In CCS, October 2024.
𝜇CFI: Formal Verification of Microarchitectural Control-flow Integrity [pdf]Paper   𝜇CFI: Formal Verification of Microarchitectural Control-flow Integrity [link]URL   link   bibtex   141 downloads  
HybriDIFT: Scalable Memory-Aware Dynamic Information Flow Tracking for Hardware. Flavien Solt; and Kaveh Razavi. In ICCAD, October 2024.
HybriDIFT: Scalable Memory-Aware Dynamic Information Flow Tracking for Hardware [pdf]Paper   HybriDIFT: Scalable Memory-Aware Dynamic Information Flow Tracking for Hardware [link]URL   link   bibtex   66 downloads  
ZenHammer: Rowhammer Attacks on AMD Zen-based Platforms. Patrick Jattke; Max Wipfli; Flavien Solt; Michele Marazzi; Matej Bölcskei; and Kaveh Razavi. In USENIX Security, August 2024.
ZenHammer: Rowhammer Attacks on AMD Zen-based Platforms [pdf]Paper   ZenHammer: Rowhammer Attacks on AMD Zen-based Platforms [link]URL   link   bibtex   188 downloads  
Cascade: CPU Fuzzing via Intricate Program Generation. Flavien Solt; Katharina Ceesay-Seitz; and Kaveh Razavi. In USENIX Security, August 2024.
Cascade: CPU Fuzzing via Intricate Program Generation [pdf]Paper   Cascade: CPU Fuzzing via Intricate Program Generation [link]URL   link   bibtex   375 downloads  
HiFi-DRAM: Enabling High-fidelity DRAM Research by Uncovering Sense Amplifiers with IC Imaging. Michele Marazzi; Tristan Sachsenweger; Flavien Solt; Peng Zeng; Kubo Takashi; Maksym Yarema; and Kaveh Razavi. In ISCA, July 2024. Nominated for the Best Paper Award
HiFi-DRAM: Enabling High-fidelity DRAM Research by Uncovering Sense Amplifiers with IC Imaging [pdf]Paper   HiFi-DRAM: Enabling High-fidelity DRAM Research by Uncovering Sense Amplifiers with IC Imaging [link]URL   link   bibtex   88 downloads  
  2023 (1)
REGA: Scalable Rowhammer Mitigation with Refresh-Generating Activations. Michele Marazzi; Flavien Solt; Patrick Jattke; Kubo Takashi; and Kaveh Razavi. In S&P, May 2023. Patent pending
REGA: Scalable Rowhammer Mitigation with Refresh-Generating Activations [pdf]Paper   REGA: Scalable Rowhammer Mitigation with Refresh-Generating Activations [link]URL   link   bibtex   159 downloads  
  2022 (3)
RemembERR: Leveraging Microprocessor Errata for Design Testing and Validation. Flavien Solt; Patrick Jattke; and Kaveh Razavi. In MICRO, October 2022.
RemembERR: Leveraging Microprocessor Errata for Design Testing and Validation [pdf]Paper   RemembERR: Leveraging Microprocessor Errata for Design Testing and Validation [link]URL   link   bibtex   71 downloads  
CellIFT: Leveraging Cells for Scalable and Precise Dynamic Information Flow Tracking in RTL. Flavien Solt; Ben Gras; and Kaveh Razavi. In USENIX Security, August 2022. Patent pending
CellIFT: Leveraging Cells for Scalable and Precise Dynamic Information Flow Tracking in RTL [pdf]Paper   CellIFT: Leveraging Cells for Scalable and Precise Dynamic Information Flow Tracking in RTL [link]URL   link   bibtex   75 downloads  
ProTRR: Principled yet Optimal In-DRAM Target Row Refresh. Michele Marazzi; Patrick Jattke; Flavien Solt; and Kaveh Razavi. In S&P, May 2022. Patent pending, ETH Spark Award Nomination, CSAW Europe finalist
ProTRR: Principled yet Optimal In-DRAM Target Row Refresh [pdf]Paper   ProTRR: Principled yet Optimal In-DRAM Target Row Refresh [link]URL   link   bibtex   53 downloads  
  2020 (2)
Energy Efficient Heartbeat-Based MAC Protocol for WBAN Employing Body Coupled Communication. Flavien Solt; Robin Benarrouch; Guillaume Tochou; Olivér Facklam; Antoine Frappé; Andreia Cathelin; Andreas Kaiser; and Jan Rabaey. IEEE Access. October 2020.
link   bibtex  
Heartbeat-Based Synchronization Scheme for the Human Intranet: Modeling and Analysis. Robin Benarrouch; Ali Moin; Flavien Solt; Antoine Frappé; Andreia Cathelin; Andreas Kaiser; and Jan Rabaey. In ISCAS, October 2020.
link   bibtex